1. Field of the Invention
The present invention relates to a waveform generator that generates an arbitrary waveform.
2. Description of the Related Art
A test apparatus for testing a semiconductor device (hereinafter, referred to as a Device Under Test: DUT) has a function of generating a signal having an arbitrary waveform, which is supplied to the DUT (See Patent Documents 1 to 4).
In FIG. 6 of Patent Document 2, a waveform generator is disclosed, the waveform generator comprising: a set pulse generator that generates a set pulse; a reset pulse generator that generates a reset pulse; and a flip-flop that is set by the set pulse and reset by the reset pulse. According to the technique, in each of the set pulse generator and the reset pulse generator, L multiple variable delay elements that delay pulse signals having the same frequency as the reference clock are provided, where L is an integer of 2 or greater. Different delay amounts are set in the multiple variable delay elements. Outputs from the multiple variable delay elements in the set pulse generator are multiplexed and then inputted to the set terminal of the flip-flop; and outputs from the multiple variable delay elements in the reset pulse generator are multiplexed to be inputted to the reset terminal thereof. By controlling the delay amount of each of the variable delay elements, the flip-flop can output a signal having an arbitrary waveform and having, at most, a frequency obtained by multiplying the reference clock by L.    [Patent Document 1] Japanese Patent Application Publication No. H 10-232271    [Patent Document 2] Japanese Patent Application Publication No. H 11-304888    [Patent Document 3] Japanese Patent Application Publication No. 2000-39469    [Patent Document 4] Japanese Patent Application Publication No. 2006-11287
In the technique in FIG. 6 of Patent Document 2, each of the variable delay elements delays a pulse signal having the same frequency as that of the reference clock. Accordingly, with the same variable delay elements, two delay amounts cannot be set within the frequency of a single reference clock.
This condition is called a “proximity limit” in the present description. In a conventional architecture, when violating the proximity limit, the delay that is set for the second time in the same variable delay circuit has to be neglected, and hence the intended waveform cannot be generated. Also, there occurs a problem that a bit rate of a signal is smaller than a value obtained by multiplying the reference clock by L.